library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
 
entity tb_CNT is
end tb_CNT ; 
 
architecture testbench of tb_CNT  is
--Component Declaration for the Unit Under Test(UUT)
  component MY_CNT 
     port(
            CLK,RESET: in std_logic; 
            D_IN: in std_logic_vector(7 downto 0);
             LOAD: in std_logic; 
            CE  :in std_logic; 
            UPDW:in std_logic; 
            Q_OUT:out std_logic_vector(7 downto 0) 
            ); 
  end component; 
  
--Inputs 
  signal CLK: std_logic := '0';
  signal RESET: std_logic := '0'; 
  signal D_IN: std_logic_vector(7 downto 0):=(others =>'0'); 
  signal LOAD: std_logic := '0';
  signal CE: std_logic := '0';
  signal UPDW: std_logic := '0';
--Outputs
  signal Q_OUT: std_logic_vector(7 downto 0);
  constant CLK_period: TIME:=1ns; 
begin 
--例化計數(shù)器模塊
  UUT: MY_CNT  port map(
        CLK => CLK, 
        RESET=>RESET, 
        D_IN=>D_IN,
         LOAD=>LOAD, 
        CE =>CE, 
        UPDW=>UPDW,
        Q_OUT=>Q_OUT
        ); 
--時鐘實現(xiàn)模塊
--上面定義了CLK period時間常量來表示時鐘周期
--以下通過一個process來實現(xiàn)時鐘
  CLK_process: process
  begin 
    CLK <= '0'; 
    wait for CLK_period/2; 
    CLK <= '1';  
    wait for CLK_period/2; 
  end process; 
--其它信號量的控制
--時序邏輯的仿真的時間單位都為CLK周期來實現(xiàn)的
--所以將時鐘周期定義為常量是個很方便的做法

stim_proc:process
begin
  --hold reset state for 100ms.
wait for 100ms; 

wait for CLK_period*10; 
  --insert stimulus here.
  end process;       
end testbench; 

--File process
file_process:process
    file file_out: text is out "data_out.txt";
    file file_in : text;
    variable fstatus: FILE_OPEN_STATUS;
    --定義文件狀態(tài)指示變量，一般有OPEN OK, STATUS ERROR, NAME ERROR, MODE ERROR 四種狀態(tài);
    variable count: integer:=5;
    --定義integer 型寫入數(shù)據(jù)；
    variable stringdata:string (5 downto 1):="whwhn";
    --定義string 型寫入數(shù)據(jù);
    variable vectordata: bit_vector(5 downto 0):="001000";
    --定義bit_vector 型寫入數(shù)據(jù);
    variable value:std_logic_vector(3 downto 0):="1111";
    --定義std_logic_vector型的寫入數(shù)據(jù);
    variable stddata:std_logic;
    variable BUFO:LINE;
begin
    --file_open(fstatus,file_out,"data_out.txt",write_mode);
    file_open(fstatus,file_in,"data_in.txt",read_mode);

    
    --LINE類型：為std庫中TEXTIO文件中的定義
    for i in 0 to 29 loop
        readline (file_in,BUF0);
        read(BUF0,stddata);
        LOAD<= stddata;
        wait for CLK_period;
    end loop;